1. Field of the Invention
The present invention relates to a semiconductor device, more particularly, to a semiconductor device having an array type semiconductor chip.
2. Description of the Related Art
It has been necessary that various kinds of array type semiconductor devices are developed although the production of them is not so many. Therefore, it has been required to design such semiconductor devices during a short period of time in low cost. Particularly, it must be carried out to perform a layout design that includes an arrangement of circuit blocks, interconnections among circuit blocks, etc.
A conventional array type semiconductor device will be described with reference to FIGS. 4 and 5. As shown in FIG. 4, the device comprises an array type semiconductor chip 51 mounted on an island 53, a plurality of leads 52 connected to external terminals, bonding wires 54 for connecting electrode pads (not shown), provided on the surface of the chip 51, to the leads 52, respectively, and a resin layer 55 for encapsulating the components 51, 52, 53, and 54. The leads 52 and the island 53 are unitarily formed by a metal plate.
FIG. 5 is a plan view showing that portion of the array type semiconductor chip 51 enclosed by broken lines in FIG. 4. As shown in FIG. 5, a plurality of electrode pads 56 are provided on the peripheral portions of the chip 51. The electrode pads 56 are connected to the leads 52 by the bonding wires 54, respectively.
The array type semiconductor chip 51 will be described in more detail. The chip 51 includes a plurality of circuit blocks, among which are connected by wiring layers. For designing the chip, the circuit blocks are arranged in the optimum positions the chip 51, and then wiring patterns for connecting the circuit blocks are provided.
For performing the arrangement of the circuit blocks and the layout design of the wiring layers, it is desirable that the wiring patterns are included in several kinds of wiring patterns. However, it is necessary to newly produce wiring patterns in various kinds of chips produced in small quantities. Further, for designing the wiring patterns, it is necessary to decrease the wiring area occupying the greater part of the chip size, thereby reducing the chip size. However, the wiring patterns will be complicated with increasing the integration density. Therefore, since the design period of the wiring pattern is increased, the cost required for designing the wiring patterns may be increased, thereby further increasing the cost for the array type semiconductor device.